1. Field of the Invention
The invention relates to a method for fabricating integrated structure, and more particularly, to a method of forming a through-substrate structure with through-substrate via and through-substrate conductor having void therein.
2. Description of the Prior Art
Through-silicon via technique is a novel semiconductor technique, which mainly servers to solve the problem of electrical interconnection between chips and belongs to a new 3D packing field, and also produces products that meet the market trends of “light, thin, short and small” through the 3D stacking technique and also provides wafer-level packages utilized in micro-electronic mechanic system (MEMS), and photoelectronics and electronic devices.
The through-silicon via technique drills holes in the wafer by etching or laser then fills the holes with conductive materials, such as copper, polysilicon or tungsten to form vias, i.e. conductive channels connecting inner regions and outer regions. The wafer or the dice is then thinned to be stacked or bonded together to form a 3D stack IC. By using this approach, the wire bonding procedure could be omitted. Using etching or laser to form conductive vias not only omits the wire bonding but also shrinks the occupied area on the circuit board and the volume for packing. The inner connection distance of the package created by using the through-silicon via technique, i.e. the thickness of the thinned wafer or the dice, is much shorter compared with the conventional stack package of wire bonding type. The performance of the 3D stack IC would therefore be much better in many ways, including faster transmission, and lower noise. The advantage of the shorter inner connection distance of the through-silicon via technique becomes much more pronounced in CPU, flash memory and memory card. As the 3D stack IC could be fabricated to equate the size of the dice, the utilization of through-silicon via technique becomes much more valuable in the portable electronic device industry.
However in the state of the art there are still key issues which need to be resolved in order to integrate these TSV connections in a reliable way with good device performances: The utilization of a through-silicon bar-like structure surrounding the through-silicon via for shielding purpose typically results in overly small critical dimension as the dimension of through-silicon via decreases, causing poor plating performance. Hence, how to resolve issue in the fabrication of through-silicon structure has become an important task in this field.